We are looking for talented digital design engineers to lead the digital section development of cutting edge mixed-signal communication ICs. The candidate must have a proven record of handling all aspects of the front end of the digital ASIC flow in state-of-the-art CMOS process technologies including micro architecture design, RTL implementation, design verification, and power optimization. Experience with embedded MCU system is particularly helpful.

·       Work with the analog leads to define and implement digital architectures supporting mixed-mode IPs

·       Support the SW/HW architecture design and implementation around embedded micro-controller and/or RISC processor in the chip

·       Working with the verification leads to support definition/execution of verification plans at the block/chip level

·       Run front end of the ASIC flow including logic synthesis under multi clock-domain design constraints
·       perform static timing analysis, power estimation and optimization, CDC/Linting and logic equivalence checking

·       Supporting FW team during chip bring-up and validation

·       MS in electrical/computer engineering with minimum 5 years of digital ASIC experience 

·       Proficient in Verilog and/or System Verilog

·       Comfortable working with digital CAD tools (Cadence and/or Synopsys)

·       Working knowledge with at least one scripting language such as TCL/Python/Perl

·       Excellent written and verbal communication skills

·       The ideal candidate would have prior experience with RISC-V microcontroller and/or ARM processor and their peripherals

·       Basic understanding of Digital Signal Processing and Communication Systems is a plus

Company Perks & Benefits

·       Competitive salary with annual base pay range $120k ~ $200k

·       Equity award at a rapid growth startup company

·       Medical, dental, and vision benefits

·       401k Plan and matching

·       Paid parental leave

·       Flexible paid time off