As the lead CAD engineer you will be responsible for managing the environment and tools for a mixed-signal IC design team. You will be responsible for defining new or improving existing IC design methodologies and flows. These include design data management/tracking, analog/digital verification flows and implementing safety measures to reduce risk and ensure data integrity throughout IC design cycle. You will also need to develop tools and systems that improve design efficiency and safety, such as data backup, license management, simulation result aggregation, and automated data integrity checking.
Minimum Qualifications
· Degree in EE, with knowledge of IC design fundamentals: basic analog circuit topologies, digital circuit building blocks, transistor device physics, etc.
· Full proficiency in Python and Skill scripting languages, and familiarity with system Verilog, shell (csh/bash), Perl, and Tcl
· Comprehensive understanding of analog-on-top and/or digital-on-top tape-out flows, from design entry to gds generation
· Knowledge of analog verification tools including LVS/DRC, physical extraction, and 3D modeling
· Knowledge of digital backend analysis and verification, such as timing, equivalence checking, and power optimization
Preferred Qualifications
· Able to produce excellent documentation (web pages, wiki, etc)
· Strong understanding of linux systems, including networking, process management/system monitoring
· Familiarity with version control systems, and experience designing, testing and deploying large systems and tools to a team
· Experience with distributed computing, job queues, and resource pools
· Experience with Cadence suite of custom analog tools: virtuoso, QRC, PVS/Pegasus
· Experience with Cadence digital design tools: Xcelium, Genus, Innovus
Company Perks & Benefits
· Competitive salary with annual base pay $120k ~ $200k
· Equity award at a rapid growth startup company
· Medical, dental, and vision benefits
· 401k Plan
· Paid parental leave
· Flexible paid time off