Sr. Physical Design Engineer
Responsibilities:
- Responsible for physical implementation of custom ASIC in advanced processes
- Perform the following jobs or tasks:
- Block level floorplan
- Clock tree synthesis
- Place & Route
- STA, timing closure
- DRC/LVS/ERC clean up
- Low power design
- TCL/TK, CSH, Perl programing
Qualifications:
- Education: Bachelor’s Degree or above in Electronics Engineering or Computer Science from a top university.
- At least five (5) years of industry experience on physical implementation on netlist 2 gds flow in 16nm or smaller process node
- Good communication and problem solving skills.
- Positive, Active, Collaborative, Self-motivated
- Strong customer orientation skills are highly desirable.