Sr. Digital Verification Engineer 


  • Work with the architecture team and design engineers to fully understand the assigned functional blocks and develop a test plan based on the architecture of the ASIC.
  • Implement test benches and test cases with UVM methodology or C co-simulation environment
  • Responsible for functional verification on block and full chip level, work with design engineers to achieve design objectives.
  • Conduct and maintain verification methodologies such as regression, code coverage and functional coverage analysis.
  • Participate in RTL and post-layout gate level simulation with SDF back-annotation.
  • Participate in pre-silicon validation using FPGA platform, and post-silicon bring up on EVB.


  • MSEE or equivalent with 3+ years relevant verification experience.
  • Working experience with System Verilog and advanced UVM/VMM/OVM methodologies and have been through minimally 2 silicon tape-outs.
  • Knowledge of OOPs concepts and C++.
  • Verification experience with mixed signal design and C/SystemC/C++ co-simulation environment is a plus.
  • Domain knowledge in networking ASICs, such as Ethernet PCS/PMA layer or higher layer in IP stack is definitely a plus.
  • Experienced in one or more scripting languages, such as Perl, TCL, Python and Makefile.
  • Good English communication and documentation skill.