Sr. Digital Frontend Designer

Job Responsibilities

  • Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
  • Design documentation
  • Test plan generation

Job Requirements

  • MS degree of EE with minimum of 3 years of work experience
  • Familiar with Verilog RTL design and Cadence design flow
  • Familiar with unix / linux and one or more scripting languages (Perl, Python, tcl etc.)
  • Experience with UVM verification flow is preferred
  • Good communication skill
  • Experience with Ehternet Packet Parser/Classification design preferred