Principal Verification Engineer

Job Responsibility

  • Architect and deploy verification environment and flow
  • Write test plans for high speed communication SoC using UVM and system verilog
  • Create regression flow using SQL database and job queue
  • Create block level behavioral models


  • BS or MS in EE / CS with minimum 15 years of experience
  • Familiar with Cadence design flow
  • Experience in using PLI routines
  • Strong in scripting language