We are looking for talented digital design engineers to develop cutting edge high-speed communication ICs. The role involves the front end of the digital ASIC flow in state-of-the-art CMOS process technologies including micro architecture design, RTL implementation, verification, logic synthesis under multi-clock domain design constraints, CDC/Linting, logic equivalence checking and timing analysis.
Responsibilities
· Working with the system lead to architect and implement high speed and low power micro-architectures for various fixed-point DSP/FEC subsystems
· Working with the analog lead to define and implement digital architectures in areas such as ADC/DAC calibration, AGC and adaptive equalization, and clock and data recovery
· Working with the verification lead to support definition/execution of verification plans at the block/chip level
· Supporting the FW team during chip bring up and validation
· Supporting front end of the ASIC flow including logic synthesis, definition of multi-clock-domain design constraints, performing static timing analysis and optimizing for speed/power
Requirements
· MS or Ph.D in electrical/computer engineering with minimum 2 years of digital ASIC experience
· Good understanding of signal processing and forward error correction algorithms and their low power architectures
· Good handle on fixed point data path analysis
· Proficient in Verilog and/or System Verilog
· Comfortable with programming language such as Python/C++
· Excellent written and verbal communication skills
Preferred (but not required):
· Conceptual understanding of various components in a digital communication system such as, Viterbi Algorithm, SOVA, and FFT/IFFT
Company Perks & Benefits
· Competitive salary
· Equity award at a rapid growth startup company
· Medical, dental, and vision benefits
· 401k Plan
· Paid parental leave
· Flexible paid time off